1. Field of the Invention
This invention relates to an image display apparatus (hereinafter referred to as "display monitor") having an image display means such as a cathode ray tube (hereinafter referred to as "CRT" for short) and the like, which displays images, a computer apparatus (hereinafter referred to as "host computer") for controlling the display monitor, a computer system equipped with the display monitor and the host computer and a control method of the computer system equipped with the display monitor and the host computer.
2. Description of the Prior Art
FIG. 1 is a block diagram showing a prior art display monitor, a prior art host computer and a prior art computer system equipped with both of them. In FIG. 1, reference numeral 1 designates a display monitor (image display apparatus) for displaying images; reference numeral 2 designates a host computer (computer apparatus) for controlling the display monitor; reference numeral 3 designates a keyboard (manipulation-inputting means) for inputting various indicating signals to the host computer 2; reference sign S1 designates video signals outputted from the host computer 2; reference sign S2 designates synchronizing signals outputted from the host computer 2; reference numeral 4 designates an input terminal for receiving the video signals S1; reference numeral 5 designates an input terminal for receiving the synchronizing signals S2; reference numeral 6 designates a CRT (cathode ray tube) for displaying images according to video signals; reference numeral 7 designates the cathode electrode of the CRT 6; reference numeral 8 designates the heater electrode of the CRT 6; reference numeral 9 designates the anode terminal of the CRT 6; reference numeral 10 designates the deflecting yoke of the CRT 6; reference numeral 11 designates the degaussing coil (degaussing means) of the CRT 6; reference numeral 12 designates a video-signal-amplifying circuit (video-signal-supplying means) for receiving the video signals S1, and for deforming and amplifying the video signals S1 to a form suitable for displaying images on the CRT 6, and then for outputting the deformed and amplified video signals S1 to the cathode electrode 7 of the CRT 6; reference numeral 13 designates a deflecting and high-voltage-impressing circuit (driving-voltage-impressing means) for receiving the synchronizing signals S2 and for impressing deflecting voltages to the deflecting yoke 10 of the CRT 6 and high voltages to the anode terminal 9 of the CRT 6 respectively; reference numeral 14 designates a power source circuit (driving-voltage-impressing means) for supplying power voltages for actuating the video-signal-amplifying circuit 12, the deflecting and high-voltage-impressing circuit 13, a degaussing circuit (degaussing means) 15 and a controlling circuit (controlling means) 17 respectively, and for supplying electric power for heating to the heater electrode 8 of the CRT 6; reference numeral 15 designates the degaussing circuit for supplying a degaussing current from the power source circuit 14 to the degaussing coil 11 of the CRT 6; reference sign 15r designates a relay installed in the degaussing circuit 15; reference numeral 16 designates a switch group (adjusting means) for manipulating the input of instructions concerning the brightness, chromaticity and faceplate sizes of the images displayed on the CRT 6, degaussing operations and the like to the controlling circuit 17; and reference numeral 17 designates the controlling circuit for receiving the synchronizing signals S2 and the manipulated inputs from-the switch group 16 and further receiving the supplement of the power voltage from the power source circuit 14, and then for supplying each controlling signal to the video-signal-amplifying circuit 12, the deflecting and high-voltage-impressing circuit 13, the power source circuit 14 and the degaussing circuit 15.
FIG. 2 is a block diagram showing an internal construction of the controlling circuit 17. In FIG. 2, reference numeral 20 designates a one-chip microcomputer (hereinafter referred to as "MC" for short) having a built-in read only memory (hereinafter referred to as "ROM" for short) 201 and a built-in random access memory (hereinafter referred to as "RAM" for short) 202; and the HSYNC terminal and the VSYNC terminal of the MC 20 are connected to the input terminal 5 for the synchronizing signals S2, and horizontal synchronizing signals (hereinafter referred to as "H synchronizing signals" for short) and vertical synchronizing signals (hereinafter referred to as "V synchronizing signals" for short) are inputted to the HSYNC terminal and the VSYNC terminal respectively. Moreover, the switch group 16 are connected to input terminals 203, and the manipulated inputs of the switch group 16 are inputted from the input terminals 203. Furthermore, the output terminal of degaussing signals (hereinafter referred to as "DEGAUSS" signals), which control the degaussing operation of the CRT 6, of MC 20 is connected to the relay-driving input terminal of the degaussing circuit 15; and the output terminal of suspending signals (hereinafter referred to as "SUSPEND" signals), which suspends the power voltage supply to the deflecting and high-voltage-impressing circuit 13 from the power source circuit 14, and the output terminal of complete off signals (hereinafter referred to as "COMPLETE OFF" signals), which suspends the power voltage supply to the heater electrode 8 of the CRT 6, too, are connected to the power source circuit 14. Reference numeral 21 designates an electrically erasable/programmable ROM (hereinafter referred to as "E.sup.2 PROM" for short) connected to the MC 20; reference numeral 22 designates a D/A converter, which converts digital signals from the MC 20 into analogue signals, connected to the MC 20. The output terminal of contrast signals (hereinafter referred to as "CONTRAST" signals), which adjust the brightness of the images displayed on the CRT 6, of the D/A converter 22 is connected to the brightness-controlling input terminal of the video-signal-amplifying circuit 12; and each output terminal of red signals' gain-adjusting signals (hereinafter referred to as "R-GAIN" signals), green signals' gain-adjusting signals (hereinafter referred to as "G-GAIN" signals) and blue signals' gain-adjusting signals (hereinafter referred to as "B-GAIN" signals) of the D/A converter 22 is connected to the red-gain-controlling input terminal, the green-gain-controlling input terminal and the blue-gain-controlling terminal of the video-signal-amplifying circuit 12 respectively. The output terminals of the horizontal-width-adjusting signals (hereinafter referred to as "H-SIZE" signals), which adjusts the horizontal widths of the images displayed on the CRT 6, and the vertical-width-adjusting signals (hereinafter referred to as "V-SIZE" signals), which adjusts the vertical widths of the images, of the D/A converter 22 are connected to the horizontal-width-controlling input terminal and the vertical-width-controlling input terminal of the deflecting and high-voltage-impressing circuit 13 respectively.
FIG. 3 is a block diagram showing an internal construction of the host computer 2. In FIG. 3, reference numeral 31 designates a central processing unit (hereinafter referred to as "CPU" for short) (a central controlling means, an indicating-signal-outputting means) which executes various kinds of arithmetic processes; and reference numeral 32 designates a clock-generating circuit for generating clock signals, and the clock-generating circuit 32 supplies the generated clock signals to the CPU 31. Reference sign CB designates a control bus for giving and receiving control signals between the CPU 31 and other construction elements; reference sign DB designates a data bus for giving and receiving data between the CPU 31 and other construction elements; and reference sign AB designates an address bus for giving and receiving address signals between the CPU 31 and other construction elements. Reference numeral 33 designates a RAM (memorizing means) for memorizing data and the like temporarily; reference numeral 34 designates a ROM (memorizing means) for memorizing system programs for controlling the operation of the host computer 2 and various kinds of data over a long period of time; and reference numeral 35 designates a memory controller for controlling the operation of the RAM 33 and the ROM 34. Reference numeral 36 designates a bus controller for controlling the operation of signals on the control bus CB, the data bus DB and the address bus AB, the bus controller 36 being connected to the control bus CB, the data bus DB, the address bus AB and the memory controller 35. Reference numeral 37 designates an interruption controller for controlling interruption operation; reference numeral 38 designates a timer for time-controlling; reference numeral 30 designates a mouse (manipulation-inputting means) for inputting indicating signals for executing necessary selection on the CRT 6 of the display monitor 1; and reference numeral 39 designates a keyboard/mouse controller (terminal-controlling means) for receiving manipulated input signals from the keyboard 3 and the mouse 30. Reference numeral 41 designates a hard disc apparatus (memorizing means) for memorizing system programs for controlling the operation of the host computer 2, and the like; reference numeral 40 designates a disc controller (terminal-controlling means) for controlling the hard disc apparatus 41; reference numeral 43 designates a printer; reference numeral 42 designates a serial port (communicating means) for inputting and outputting bit-serial data for the communication in conformity to the RS 232C standard, the serial port 42 being connected to the printer 43, a modem (not shown in FIG. 3) and the like. Reference numeral 44 designates a video controller (terminal-controlling means) transmitting synchronizing signals and video signals for controlling the display monitor 1; and reference numeral 45 designates an expanding slot for adding additional functions.
Next, the operation will be described. FIG. 4 is a flowchart showing a part of the operation of the MC 20 of the controlling circuit 17 of the display monitor 1. Hereafter, the operation of these prior art display monitor 1, host computer 2 and computer system will be described according to FIG. 4.
When the electric power of the display monitor 1 is turned on, the MC 20 reads out the image-controlling data such as brightness data, chromaticity data, faceplate size data of the images and the like memorized in the E.sup.2 PROM 21 and writes them into the RAM 202 (STEP ST60). Next, MC 20 judges whether both the H synchronizing signals and the V synchronizing signals to be inputted from the video controller 44 of the host computer 2 are actually inputted or not (STEP ST61), and the MC 20 executes the COMPLETE OFF mode process when both of the synchronizing signals are not inputted (STEP ST62) . In this COMPLETE OFF mode process, the MC 20 makes both the SUSPEND signal output and COMPLETE OFF signal output, which are ordinarily in the "L" level, be in the "H" level. The SUSPEND signal output changing to the "H" level makes the power source circuit 14 suspend the supplement of the power voltages to be supplied to the deflecting and high-voltage-impressing circuit 13, and the COMPLETE OFF signal output changing to the "H" level makes the power source circuit 14 suspend the supplement of the power voltage to be supplied to the heater electrode 8 of the CRT 6, too. Since the deflecting and high-voltage-impressing circuit 13 suspends the operation thereof and the power supplement to the heater is also suspended by this operation of the power source circuit 14, the CRT 6 is placed in a completely suspended state. When the COMPLETE OFF mode processes end, the MC 20 returns to the STEP ST61 and judges the existence of the H synchronizing signals and the V synchronizing signals again.
When the MC 20 judges that either or both of the H synchronizing signals and the V synchronizing signals are inputted to the MC 20 as a result of the judgement in the STEP ST61, the MC 20 judges whether only the V synchronizing signals have not been inputted or not (STEP ST63). When only the V synchronizing signals are not inputted, the MC 20 executes the SUSPEND mode processes (STEP ST64). In this SUSPEND mode, the MC 20 makes only the SUSPEND signal output be in the "H" level, and the MC 20 suspends the supplement of the power voltages of the power source circuit 14 to the deflecting and high-voltage-impressing circuit 13 alone and the MC 20 does not suspend the supplement of power voltage to the heater electrode 8 of the CRT 6. Hereby, the power consumption in the heater of the CRT 6 remains in the same level that it consumes in the ordinary driving thereof, and the consumption power is larger than that in the COMPLETE OFF mode processes. However, the SUSPEND mode processes have an advantage in that images can be begun to be displayed faster when the computer system returns to the ordinary operation thereof. When the processes of the SUSPEND mode end, the MC 20 returns to the STEP ST61 and judges the existence of the synchronizing signals and V synchronizing signals.
Moreover, the host computer 2 suspends the supplement of both the H synchronizing signals and the V synchronizing signals or only the V synchronizing signals in synchronizing signals S2 to be supplied to the display monitor 1, when the manipulation inputs from the keyboard 3 are not received for a predetermined time period in the state which the electric power thereof are turned on. The display monitor 1 moves to either waiting states of the COMPLETE OFF mode or the SUSPEND mode by detecting the variation of the synchronizing signals S2.
When both the H synchronizing signals and the V synchronizing signals are inputted to the MC 20 or only the V synchronizing signals are inputted to the MC 20, the MC 20 executes setting processes as an ordinary operation mode of the CRT 6 (STEP ST65). In this setting processes, the MC 20 cause the COMPLETE OFF signal output and the SUSPEND signal output to be in the "L" level and it causes all the output voltages from the power source circuit 14 to be in their ordinary operation states.
Next, the MC 20 examines the existence of the manipulation inputs from the switch group 16 (STEP ST66), and the MC 20 makes the W-flag, which is a requesting flag of writing data to the E.sup.2 PROM 21, be in "1" when some manipulated inputs exist (STEP ST67). Successively, the MC 20 examines whether the DEGAUSS switch in the switch group 16 is turned on or not, and the MC 20 executes the DEGAUSS outputting processes when the manipulation turning on the DEGAUSS switch was made (STEP ST69). In this DEGAUSS output processes, the MC 20 holds the DEGAUSS output signals in the "H" level for a predetermined time period. Hereby, the relay 15r in the degaussing circuit 15 is turned on for the time period when the DEGAUSS output signal is in the "H" level, and a degaussing current flows in the degaussing coil 11 of the CRT 6 from the power source circuit 14, then the CRT 6 is degaussed. After the DEGAUSS output processes are over, the MC 20 executes the processes of the STEP ST74.
In the case where the manipulation turning the DEGAUSS switch in the switch group 16 on is not detected, the MC 20 executes the increase or decrease processes of the data in the RAM 202 according to the manipulated input of the switch group 16 except for the DEGAUSS switch (STEP ST70). The MC 20 outputs the increase-or-decrease-processed data to the D/A converter 22 from the RAM 202 (STEP ST74), thereby changing the output voltages of the output signals corresponding to the manipulated inputs among each output signal of the CONTRAST output signals, the R-GAIN output signals, the G-GAIN output signals, the B-GAIN output signals, the H-SIZE output signals and the V-SIZE output signals of the D/A converter 22.
In the case where the inputting manipulation of the switch group 16 is not detected, the MC 20 examines whether the W flag is "1" or not (STEP ST71). If the W flag is not "1", namely in the case where the W flag is "0", the MC 20 executes the STEP ST74 process; and if the W flag is "1", the MC 20 writes the data on the RAM 202 into the E.sup.2 PROM 21 (STEP ST73), and then the MC 20 resets the W flag to "0" after writing the data (STEP ST73). Thus, the manipulated inputs of the switch group 16 are stored in the E.sup.2 PROM 21 and reserved therein. Next, the MC 20 outputs the data in the RAM 202 to the D/A converter 22 (STEP ST74), then the D/A converter 22 outputs controlling signals corresponding to the manipulated inputs made last to the video-signal-amplifying circuit 12. Thus, the CRT 6 continues to display images in the same displaying conditions. The MC 20 again examines the existence of the H synchronizing signals and the V synchronizing signals (STEP ST61) and continues the operation thereof after its data outputting process to the D/A converter 22.
Since the prior art display monitor, the prior art host computer, the prior art computer system and the prior art control method of the computer system were constructed as mentioned above, they had problems as follows. That is,
(1) To adjust accurately for adjusting the brightness or chromaticity of the display monitor or in case of changing the location place or the direction of the display monitor, it is required to execute the degaussing operation of its CRT. To degauss the CRT, an operator had to manipulate the DEGAUSS switch installed in the body of the display monitor, that is to say he could not manipulate the switch by using a keyboard, so the manipulation of that switch was troublesome.
(2) There were some cases that the adjustments of the display monitor were deviated from the standard or the appropriate displaying states to the object of its usage by the misoperation of an operator after a serviceman or an equipment-maintaining person in charge set the brightness, the chromaticity or the faceplate size of the display monitor. In such cases, it required much labor to restore the display monitor to the appropriate displaying state.
(3) An ordinary host computer had no function to suspend the supply of the H synchronizing signals and V synchronizing signals, and it required the equipment of some special hardware to install the suspension function in the host computer. Then, the installation of the function complicated the structure of the host computer and it was also one of the causes of raising the manufacturing cost of the host computer. Besides, it was also required on the display monitor side, to install some hardware for detecting the existence of the synchronizing signals. Thus the structure of the display monitor was made more complicated and the manufacturing cost thereof was increased.